كلية الهندسة - جامعة عين شمس, الرئيسية

الرئيسية  >  كلية الهندسة - جامعة عين شمس, الرئيسية

Digital Systems Testing and Verification

What Will Learn?

  • Course Aims
    Upon completion of the course, students will: 1. Understand what it means to verify designs at the register-transfer level. 2. Learn the various standard parts in an industrial design-verification testbench and infrastructure. 3. Learn about test writing, test coverage, and deciding when you are done testing. 4. Be competent in writing tests in SystemVerilog (which is essentially the standard language for that task).
  • Course Goals
  • Decent Work and Economic Growth
  • Industry, Innovation and Infrastructure
  • Sustainable Cities and Communities

Requirements

CSE313s AND CSE331s

Description

  • English Description

    VLSI design flow: Specifications, Architectural design (scheduling, binding/allocation), RTL design, Verification, Logic synthesis, Physical layout (floor planning, placement and routing). Verification concepts: What to verify (functional verification, timing verification, performance verification), How to verify (simulation, emulation, formal verification, semi-formal verification, Hardware/software coverification). Directed testing. Random testing. System Verilog: Data types, Arrays, Queues, Building score boards, User defined types, tasks and functions, Time variables. Testbench design: Interfaces, Modports, Clocking blocks, Timing problems, Race conditions, Program blocks, Case study, Randomization, Constraints, Constrained random testing. Assertions: Immediate assertions, Concurrent assertions. Coverage: Code coverage, Functional coverage, Bug rate, Assertion coverage, Cover groups, Coverage bins, Sampling expressions, Cross coverage. UVM: UVM tests, UVM components, UVM environments, UVM transactions, UVM agents, UVM sequences, Verification career.
  • Arabic Description

    VLSI design flow: Specifications, Architectural design (scheduling, binding/allocation), RTL design, Verification, Logic synthesis, Physical layout (floor planning, placement and routing). Verification concepts: What to verify (functional verification, timing verification, performance verification), How to verify (simulation, emulation, formal verification, semi-formal verification, Hardware/software coverification). Directed testing. Random testing. System Verilog: Data types, Arrays, Queues, Building score boards, User defined types, tasks and functions, Time variables. Testbench design: Interfaces, Modports, Clocking blocks, Timing problems, Race conditions, Program blocks, Case study, Randomization, Constraints, Constrained random testing. Assertions: Immediate assertions, Concurrent assertions. Coverage: Code coverage, Functional coverage, Bug rate, Assertion coverage, Cover groups, Coverage bins, Sampling expressions, Cross coverage. UVM: UVM tests, UVM components, UVM environments, UVM transactions, UVM agents, UVM sequences, Verification career.
  • قسم
    هندسة الحاسبات والنظم
  • الساعات المعتمدة
    3
  • الدرجات
    الإجمالي ( 100 ) = نصف العام (20) + tr.Student Activities (30 = tr.Industry 0% , tr.Project 0% , tr.Self_learning 0% , tr.Seminar 30% ) + درجة الامتحان (50)
  • الساعات
    ساعات المحاضرة: 3, ساعات التعليم: 1, ساعات المعمل: 0
  • Required SWL
    125
  • Equivalent ECTS
    5
  • 1. Janick Bergeron, Writing Testbenches using System Verilog, Springer, 2006.
  • 2. Chris Spear, System Verilog for Verification: A Guide to Learning the Testbench Language Features, 2nd Edition, Springer, 2008.
  • 3. Ray Salemi, The UVM Primer: An Introduction to the Universal Verification Methodology, Boston Light Press, 2013.