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Algorithms for Electronic Design Automation

What Will Learn?

  • Course Aims
    • By the end of this course the student will be • Understand EDA Tools Overview • Understand what is Semiconductor Industry • Familiar with ASIC Flow and Difference btw ASIC and FPGA Flow • Able to build Digital Circuit Using Verilog • Able to Create Verification Env Test Bench Coverage Assertion • Understand Functional Verification Concepts Techniques Simulation Formal Lint Assertion Coverage Stimulus Generation • Understand Logic Synthesis Design for Testability Logic Optimization Algorithm • Brief Knowledge about Back End Steps Like Floor Planning Place Route Physical Verification to Mask Creation • Familiar with some EDA Tools Simulation Static Checks Synthesis Place Route • On Hand Experience with some EDA Algorithms such as SAT BDD ATPGA
  • Course Goals
  • Decent Work and Economic Growth
  • Industry, Innovation and Infrastructure
  • Sustainable Cities and Communities

Requirements

CSE221 AND CSE243

Description

  • English Description

    Introduction to design methodologies, VLSI design automation tools, Algorithmic graph theory and computational complexity, Tractable and intractable problems, General-purpose methods for combinatorial optimization, Simulation, Selected design problems and algorithms: Logic synthesis and verification, High-level synthesis, Layout compaction, Placement and partitioning, floor planning, Routing.
  • Arabic Description

    Introduction to design methodologies, VLSI design automation tools, Algorithmic graph theory and computational complexity, Tractable and intractable problems, General-purpose methods for combinatorial optimization, Simulation, Selected design problems and algorithms: Logic synthesis and verification, High-level synthesis, Layout compaction, Placement and partitioning, floor planning, Routing.
  • Department
    Computer and Systems Engineering
  • Credit Hours
    3
  • Grades
    Total ( 100 ) = Midterm (25) + tr.Major Assessment (30 = tr.Industry 0% , tr.Project 20% , tr.Self_learning 5% , tr.Seminar 10% ) + tr.Minor Assessment (5) + Exam Grade (40)
  • Hours
    Lecture Hours: 2, Tutorial Hours: 2, Lab Hours: 0
  • Required SWL
    125
  • Equivalent ECTS
    5
  • • Course Slides
  • • Dolous Verilog Training Materials
  • • https www.chipverify.com verilog verilog tutorial
  • • Synthesis Optimization of Digital Circuits Giovanni De Micheli
  • • Logic Synthesis Optimization Tsutomu Sasao
  • • Algorithms for VLSI Design Automation Sabih H. Gerez
  • • Electronic Design Automation for IC System Design Verification Testing By Luciano Lavagno Igor L. Markov Grant Martin Louis K. Scheffe - Dolous Verilog Training Materials.