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Computer Architecture

What Will Learn?

  • Course Aims
    The aim of this course is to: - Train students on the fundamental principles of computer hardware description languages. - Provide students with the concepts of Computer input/output and related design principles. - Develop the students’ knowledge of the pipelined architectural techniques used in RISC processors. - Provide students with the principles of memory technology and related design principles. - Train students to design complex computers buses circuits. - Develop the student's knowledge of designs of a complete processor using hardware description language.
  • Course Goals
  • Decent Work and Economic Growth
  • Industry, Innovation and Infrastructure
  • Sustainable Cities and Communities

Requirements

CSE312s

Description

  • English Description

    Hardware description using Verilog: Design flow, Syntax, Data Types, Operators, Primitives, Procedural blocks, Behavioral and structure descriptions of various electronic circuits, Finite state machine modeling, Writing testbenches in Verilog. Buses: An overview of different types of buses, Synchronous and asynchronous timing diagrams, Various bus arbitration mechanisms. Serial busses: Peripheral Component Interconnect (PCI) and Peripheral Component Interconnect Express (PCIe), Peripheral and communication protocols, I/O module functionality and techniques, Interrupt controller, Direct Memory Access (DMA). Memory technologies: Static RAM (SRAM), Dynamic RAM (DRAM), Disk storage. Basics of caches. Measuring and improving cache performance. Dependable memory hierarchy. Virtual machines. Virtual memory.
  • Arabic Description

    Hardware description using Verilog: Design flow, Syntax, Data Types, Operators, Primitives, Procedural blocks, Behavioral and structure descriptions of various electronic circuits, Finite state machine modeling, Writing testbenches in Verilog. Buses: An overview of different types of buses, Synchronous and asynchronous timing diagrams, Various bus arbitration mechanisms. Serial busses: Peripheral Component Interconnect (PCI) and Peripheral Component Interconnect Express (PCIe), Peripheral and communication protocols, I/O module functionality and techniques, Interrupt controller, Direct Memory Access (DMA). Memory technologies: Static RAM (SRAM), Dynamic RAM (DRAM), Disk storage. Basics of caches. Measuring and improving cache performance. Dependable memory hierarchy. Virtual machines. Virtual memory.
  • Department
    Computer and Systems Engineering
  • Credit Hours
    3
  • Grades
    Total ( 100 ) = Midterm (20) + tr.Student Activities (30 = tr.Industry 0% , tr.Project 10% , tr.Self_learning 0% , tr.Seminar 20% ) + Exam Grade (50)
  • Hours
    Lecture Hours: 2, Tutorial Hours: 2, Lab Hours: 0
  • Required SWL
    125
  • Equivalent ECTS
    5
  • - D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Elsevier, 2013, Fifth Edition
  • - Computer Organization and Architecture (9th Edition) (William Stallings Books on Computer and Data Communications) 2016, 9th Edition - D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Elsevier, 2013, Fifth Edition.