كلية الهندسة - جامعة عين شمس, الرئيسية

الرئيسية  >  كلية الهندسة - جامعة عين شمس, الرئيسية

Electronic Design Automation

What Will Learn?

  • Course Aims
    • By the end of this course the student will be • Understand EDA Tools Overview • Understand what is Semiconductor Industry • Familiar with ASIC Flow and Difference btw ASIC and FPGA Flow • Able to build Digital Circuit Using Verilog • Able to Create Verification Env Test Bench Coverage Assertion • Understand Functional Verification Concepts Techniques Simulation Formal Lint Assertion Coverage Stimulus Generation • Understand Logic Synthesis Design for Testability Logic Optimization Algorithm • Brief Knowledge about Back End Steps Like Floor Planning Place Route Physical Verification to Mask Creation • Familiar with some EDA Tools Simulation Static Checks Synthesis Place Route • On Hand Experience with some EDA Algorithms such as SAT BDD ATPGA
  • Course Goals
  • Decent Work and Economic Growth
  • Industry, Innovation and Infrastructure
  • Sustainable Cities and Communities

Requirements

CSE313s AND CSE333s

Description

  • English Description

    Overview of graph algorithms and digital design methodologies, Tour of VLSI design automation tool requirements, Computational complexity/Tractable and Intractable problems, Layout compaction, Placement and partitioning, Floor planning, Routing, Simulation of VLSI circuits, Logic synthesis, Verification, Static timing analysis, Simulation using direct/iterative methods, Analysis and optimization of VLSI circuits and systems with emphasis on computational realizations and optimization.
  • Arabic Description

    Overview of graph algorithms and digital design methodologies, Tour of VLSI design automation tool requirements, Computational complexity/Tractable and Intractable problems, Layout compaction, Placement and partitioning, Floor planning, Routing, Simulation of VLSI circuits, Logic synthesis, Verification, Static timing analysis, Simulation using direct/iterative methods, Analysis and optimization of VLSI circuits and systems with emphasis on computational realizations and optimization.
  • قسم
    هندسة الحاسبات والنظم
  • الساعات المعتمدة
    2
  • الدرجات
    الإجمالي ( 100 ) = نصف العام (20) + tr.Student Activities (30 = tr.Industry 0% , tr.Project 10% , tr.Self_learning 0% , tr.Seminar 20% ) + درجة الامتحان (50)
  • الساعات
    ساعات المحاضرة: 2, ساعات التعليم: 1, ساعات المعمل: 0
  • Required SWL
    100
  • Equivalent ECTS
    4
  • • Course Slides
  • • Dolous Verilog Training Materials
  • • https www.chipverify.com verilog verilog tutorial
  • • Synthesis Optimization of Digital Circuits Giovanni De Micheli
  • • Logic Synthesis Optimization Tsutomu Sasao
  • • Algorithms for VLSI Design Automation Sabih H. Gerez
  • • Electronic Design Automation for IC System Design Verification Testing By Luciano Lavagno Igor L. Markov Grant Martin Louis K. Scheffe - Ren Haoxing and Jiang Hu. 2022. Machine Learning Applications in Electronic Design Automation. Cham Switzerland: Springer.